IDEX WB EX/MEM WB Control M MEMWB WB IF/ID EX Instruction Registers ALU Pc Instruction memory Data memory IF/ID. RegisterRs IF/ID.Register F/ID. Registert IF/ID. RegisterRd Rs Rt RI Rd EXMEM. Register ! Forwarding unit MEMWB.Registered Question 6 (10 marks) Consider the same datapath in Question 5, how can the register file be modified to resolve the data dependence between the first and fourth instructions in the following program? To demonstrate this modification, design a register file containing four two-bit registers. Time (in clock cycles) Value of CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9 register $2: 10 10 107-20 -20 -20 -20 Program execution order (in instructions) 10 10 -20 sub $2, $1, $3 IM DM Regi and $12, $2, $5 IM Reg DM or $13, $6, $2 IM Reg! DM add $14, $2,$2 IM Reg sw $15, 100($2) IM Reg Reg IDEX WB EX/MEM WB Control M MEMWB WB IF/ID EX Instruction Registers ALU Pc Instruction memory Data memory IF/ID. RegisterRs IF/ID.Register F/ID. Registert IF/ID. RegisterRd Rs Rt RI Rd EXMEM. Register ! Forwarding unit MEMWB.Registered Question 6 (10 marks) Consider the same datapath in Question 5, how can the register file be modified to resolve the data dependence between the first and fourth instructions in the following program? To demonstrate this modification, design a register file containing four two-bit registers. Time (in clock cycles) Value of CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9 register $2: 10 10 107-20 -20 -20 -20 Program execution order (in instructions) 10 10 -20 sub $2, $1, $3 IM DM Regi and $12, $2, $5 IM Reg DM or $13, $6, $2 IM Reg! DM add $14, $2,$2 IM Reg sw $15, 100($2) IM Reg Reg