IF ID 1 ns EX 2 ns MEM 4 ns WB 1.5 ns 2.5 ns a. [6 points) What is the clock cycle time in a pipelined and non-pipelined processor? b. [7 points] What is the total latency of a Load Word instruction in a pipelined and a non-pipelined process c. Suppose the MEM stage is split into two separate stages each with a latency of 2 ns. 1. [4 points) How many stages will the new processor have? [8 points] What is the total latency of a Load Word instruction in this new processor? it it belour