If possible please provide explanation

Consider the example of an unpipelined processor shown in Figure 1. We assume that the combinational logic requires 300 ps (picoseconds) to process any computation and the loading of the results in the register requires 20 ps. The maximum rate at which we could operate in this system, also called as the throughput, is given by the following formula: Instruction 1000 picosecond (20 + 300) picosecond 1 nanosecond Throughput = 3.12 GIPS, where GIPS stands for giga-instructions per second. The total time required to perform a single instruction from beginning to end is known as the latency. In this system, the latency is 320 ps. Thus, Throughput (in GIPS- 1000. Also note that each instruction 11, 12 and 13 thus requires latency ps to process latency (in picosecon completely. Suppose we divide the computation performed by our system in three stages A, B and C (see Fig. 2), where each requires 300/3- 100 ps. Then we could put pipeline registers between the stages so that each instruction moves through the system in three steps, requiring three complete clock cycles from beginning to end. In this system, we could cycle the clocks every 100 20 120 picoseconds, giving a throughput of around 8.33 GIPS Since processing a single instruction requires 3 clock cycles, the latency of this pipeline is 3 120-360 ps. 300 ps 20 ps Combinational logic Delay 320 ps el Throughput = 3.12 GIPS OC (a) Hardware: Unpipelined I1 I2 I3 Time (b) Pipeline diagram FIG. 1: Shows an unpipelined system. (Figure taken from Brvan & O'Hallaron textbook