If you can solve 1,2 and 6

1. Determine the mid-swing output voltage Yomid 2. Determine the mid-swing bias resistors R1 & R2 3. Plot Id (0 to Ydd/(Rd+Rs)) versus Vds (0 to Ydd) for the NMOS transistor for the two Vgs input voltages that bias the transistor at its minimum and mid-swing output voltage while in saturation mode. You can approximate the curves in linear and saturation modes as straight lines Note Id, Yds. Ydsat and Vgs on the graph for each of the two lines 4. Plot the circuit load line on the same Id versus Yds plot 5. Increase Yomid to 4V, without changing the output current, in two ways: a. Change Ydd - Draw a new load line for this new circuit b. Keep Ydd at 5V and decrease Rd - Draw a new load line 6. With Ydd=5V & Rd=10k12, what value of a would decrease the Vomid (a=0) by 38m V Kn=1mA/V^2 VTN=1V Lambda=0 M R1 W Rd 10k Vo M1 5V Vdd R2 W W Rs 4k 0