III. Questions (total 80 pts) 1. Write a behavioral VHDL description for a 2-to-1 multiplexer. The VHDL ENTITY construct in given as follows (Total 3 marks): LIBRARY ieee USE ieee.std_logic_1164.alli Entity mux2tol is Port ( w : IN STD LOGIC VECTOR (1 DowNTO 0); s IN STD_LOGIC; fOUT STD_LOGIC End mux2to1; (1), else output w(0). Model the multiplexer as a process block, write on If s is true then output w the VHDL ARCHITECTURE construct