I'm not good at reading ITALIC English.

I hope you to give me really detail solution

We assume that all memories are initialized by 100 and the branch result is known in an EX state. In addition, let us assume that all memory accesses are cache hit. Instruction Sequence max: Iw $to, 0(Sa0) loop: beq St1, $a1, exit addi $t1, $zero, 1 addi $t1, St1, 1 addi $a0, $a0, 4 Iw $t2, 0($a0) slt $t3, Sto, $t2 beq $t3, $zero, end_id add $t0, $zero, $t2 end_if: jloop exit: addi $t1, $zero, 0 Register $t0$t1 $t2 $t3a0 $al number Contents 0 0 0 0 1000 4 1. Identify all data hazards in the following sequence of instructions, when executed on the 5-stage pipeline d MIPS implementation without forwarding 2. Identify all data hazards in the following sequence of instructions, when executed on the 5-stage pipeline d MIPS implementation with forwarding We assume that all memories are initialized by 100 and the branch result is known in an EX state. In addition, let us assume that all memory accesses are cache hit. Instruction Sequence max: Iw $to, 0(Sa0) loop: beq St1, $a1, exit addi $t1, $zero, 1 addi $t1, St1, 1 addi $a0, $a0, 4 Iw $t2, 0($a0) slt $t3, Sto, $t2 beq $t3, $zero, end_id add $t0, $zero, $t2 end_if: jloop exit: addi $t1, $zero, 0 Register $t0$t1 $t2 $t3a0 $al number Contents 0 0 0 0 1000 4 1. Identify all data hazards in the following sequence of instructions, when executed on the 5-stage pipeline d MIPS implementation without forwarding 2. Identify all data hazards in the following sequence of instructions, when executed on the 5-stage pipeline d MIPS implementation with forwarding