Implement a 4-bit Register Module with Load Enable and Reset, verify the module. Create a clock in the test bench.

The following is the D Flip-Flop Verilog Module needed for this assisnment.

module d_flip_flop (input bit clk, input bit D, output logic Q);

always @ (posedge clk) begin

Q <= D;

end

endmodule : d_flip_flop