in = 0 1 0 0 [0] S1 [0] S2 [1] rst Rajah 4 (Figure 4) QUESTION 4 For the state diagram shown in Figure 4, (a) Design the complete Verilog code to implement it using FPGA including its testbench. Use One Hot encoding method and provide an asynchronous RST in your design. (13 marks) Complete the waveform for output "out" corresponding to the input signals shown in Figure 5 (assuming positive edge flip-flops are used). (3 marks) (b) alk | in rst out Rajah 5 (Figure 5)