In a computer system, assume that main memory accesses take 80 ns and that memory accesses are one third of all instructions. The following table shows data for caches attached to each of two processors, P and P2. Processor P Processor P2 Miss Rate 7.5% 5.0% Hit Time (cycle time) 0.8ns 1.2ns A. (20 points) Calculate the data memory-stall CPI and instruction memory-stall CPI for both P and P2? Assuming a base CPI of 1.0 for both processors without any memory stalls, which processor is faster? B. (10 points) In order to increase the number of instructions being executed by 10%, we add a second-level cache for P. If the second-level cache has 5ns hit time, how much its miss rate must be?