In designing a 32-bit byte-addressable (0,3)-GPR machine, if you choose to have only the following addressing modes supported

register

immediate

register indirect with displacement

similar to the ones shown in the class, show how each of the following addressing modes can be simulated (synthesized) by simulating the operation required in the given instruction using a sequence of your machine instructions: (assuming contents of r0 is always 0)

(a) add @(r3), (r1)-, 20(r2,r4)

(b) add 0x0123456, 8(r3), r5 (assuming a word-size operation)