In memory-mapped I/O, if a user program directly accesses actual device ports in $00008000 - $00009FFF, CPU needs to cause an exception. However, 68K has no software exception in illegal I/O port accesses in the user mode. Based on the following diagram, design and draw a logical circuit that interrupts CPU if a user program accesses $00008000 - $00009FFF.

I had submitted this question earlier but I forgot the diagram. The professor has given the class hints and I have attempted this question on my own already, bit it doesn look right.

Domicroprocesor CPU D6081 ADA 31 Encoded PLO Interne Input PLZ Priory Clements: p367 IRQI" R92 IRO ROP ROS ROS IROM FO0000000 FOR POOR I/O ports are mapped on the memory address space. Processor - Easy implementation Address decoding - More complicated DTACK delayed or synchronous bus cycle used for VO devices OS viewpoint - Can't cause a trap when a user program accesses VO ports. Yet reserve 10 ports for os accesses only with FC2, FC1, and FCO in 68K 00000000 Actual Devices 10000FFF Memory Space FCO Function code LACK FCI ace FC TACK encoder IACKI AQ LACK" AOKE TACKS" JACKA TACK" 1 AI LACK level on address A bus A3 Memory Sad Reset vector TR G+ ROP KOK Processor IVEC MC Peripheral Peripheral Interruptmk bis vel below which Interupa will not be processed Vector 5 Address bus The detailed specification is as follows: 1) Upon an access to $00008000-00009FFF under FC2-FCO = 001 or 010, asserts --IRQ6. 2) Upon receiving -IACK6, de-assert -IRQ6 and then start presenting a vector 64 or $40 to D7-DO and asserting-DTACK 3) When detecting that -IACK6 is no longer asserted, (i.e., became back high), stop presenting the D7-DO vector as well as stop asserting -DTACK. 4) Use a D flip-flop to assert, keep, and de-assert -IRQ6. 5) Use a transmission gate to present each of D7-Do to the data bus by low-activating -ENB on its top input and ENB on its bottom input. Low ENB High Low ENB ENB High