In the 4th lab, you used a verilog module to write a program for finding the twos complement of a number using behavioural modeling. Mention the usage of a wire and reg used in the sample code and the main module. Assume gate-level modeling and write the same program to find the twos complement of an eight bit numb

//Implementation of the OR-gate using verilog gate-level modeling module orgate(in1,in2,outl): // definition of a module input in1,in2; //declaration of inputs output out1: //declaration of outputs wire out2; nor a1 (out2,in1,in2)://instantiation of NOR-gate not a2(out1,out2); //instantiation of NOT-gate endmodule