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In the counter design that we've done for this lab, we frequently observe the counter values wrapping around from the maximum value to the minimum

In the counter design that we've done for this lab, we frequently observe the counter values wrapping around from the maximum value to the minimum (or vice versa), e.g., 4 1 or 1 4. If you want to design a Verilog module that can detect these, how would you approach this? In your answer, be specific about whether you would describe the module in a Moore machine or a Mealy machine

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