In the following circuit, each flip-flop has parameters: tgu = 60 ps, th = 20 ps, and talk-a = 70 ps. The delay of an XOR gate is 100 ps. There are five flip-flops and three XOR gates. There are external inputs to the first four registers. The inputs to the first XOR gate are the outputs of the first two flip-flops. The inputs to the second XOR gate are the output of the first XOR gate and the output of the third flip-flop. The inputs to the third XOR gate are the output of the second XOR gate and the output of the fourth flip-flop. The input to the fifth register is the output of the third XOR gate. (a) What is the maximum clock frequency of this circuit? (b) Redesign the circuit so that it has the same functionality but has a maximum clock frequency of 3GHz