In this assignment, you as: focuirod to desipe an thilly dedicaned architecture. $($FDA$)$ to implement the following algorithms:

xlarrax$(a+b+c)$

$y+(a+c)(c+d)$

$(1)$ Apply ooarsc$-$level restructuring ox the equation of $"x\text{'}($d$.$g$.,$ fictoring, operator grouping, renoving corman sub expessions. etc$)$ bo alfow for micimal hardware implementation. Then, derive the data fow gapts $($DFG$)$ fon your decign.

$(2)$ Design the corresponding darapath, applying the constraind resource allocation of one multiplier and one adder. Also epply as$-$late$-$as possible $($A$.$ AP$)$ register allocation.

$(3)$ Write the Verilog code for your datapath unit $($DL$)$ and the control unit $($CU$).$

$(4)$ Verify your design using Modelsim,

$(5)$ Discuss the simulatoa resulis by comparing your ouput with the output of Example $6.3(a)$