In this exercise we examine how latencies of individual components of the datapath affect the clock cycle time of the entire datapath, and how these components are utilized by instructions. Assume the following latencies for logic blocks in the datapath: a) What is the clock cycle time if we only had to support Jump instruction? b) What is the clock cycle time if the only type of instructions we need to support are R-type ALU instructions (add, and, etc.)? c) What is the clock cycle time if we must support lw and beq instructions? In this exercise we examine how latencies of individual components of the datapath affect the clock cycle time of the entire datapath, and how these components are utilized by instructions. Assume the following latencies for logic blocks in the datapath: a) What is the clock cycle time if we only had to support Jump instruction? b) What is the clock cycle time if the only type of instructions we need to support are R-type ALU instructions (add, and, etc.)? c) What is the clock cycle time if we must support lw and beq instructions