In this exercise, we will look at the different ways cache capacity affects overall performance. In general, proportional to capacity. Assume that main memory accesses take 20 ns and that cache access time is memory accesses are 36% of all instructions. The following table shows data for L1 caches attached to each of two processors, P1 and P2. Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock frequency? What is the Average Memory Access Time for P1 and P2 [AMAT = hit time + miss rate * miss penalty] Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster? Extra credits for the following two questions For the next two problems, we consider the addition of an L2 cache to P1 to presumably make up for its limited L1 cache capacity. Use the L1 cache capacities and hit times from the previous table when solving these problems. The L2 miss rate indicated is its local miss rate. L2 Size L2 Miss Rate. What is the AMAT for Pl with the addition of an L2 cache? Is the AMAT better or worse with the L2 cache? Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 with the addition of an L2 cache