In this experiment, students have to modify the design of their pipelined processor implementation in experiment 7 to test the program shown in Table 3. Note that the program includes two new instructions: SGT (set if greater) and SGTI (set if greater immediate). Examples of these instructions is as follows: SGT R1, R2, R3 /l/ set R1=1 if R2>R3, otherwise R1=0 SGTI R1, R2, 100 /l/ set R1=1 if R2 >100. otherwise R1=0 Unlike previous experiments, this is not a guided experiment, i.e., students are free to make decisions on how to modify all modules in their processor. However, you are not allowed to remove any of the old instructions or start a new implementation from scratch. Students are expected to extend their processor implementation in the lab. Stepl: In Table 1. describe the change you did for each file (if any). Note that there are some files where modifications are not needed. Table 1: Verilog files File Modified Changes Description (yeso)? no no no Library439.v Exp 2 FA and MUX8_1.v Exp 2 ALUS. Exp 3 REG32 and MUX32_1.v Exp 3 Decoders and RegFile.v Instruction_memory.v DataMem.v Control Unit.v Exp6 modules.v Exp7 modules.v Piplining_Procssor.v yes Loaded the program in Table 3 no Step2: In Table 2. add new rows or columns to show the changes you did on the control unit. Highlight your changes in yellow, bold color. Table2: Truth Table for the Control Unit instruction opcode function aluop[2] aluop[1] aluop[0] alusrc [U]ispa.1 [0].sphat memtoreg[1] regwrite memtoreg[0] memread memwrite jump pesre branch 0 1 00 000 0 0 1 o 1 0 1 0 0 100 1 0 1 0 1 0 o ooo Ooo 000 0 0 0 0 ololo 0 1 0 0 0 0 1 1 1 0 0 olololololololo 1 0 0 1 0 1 0 0 1 0 1 ooooooooo 1 0 0 1 0 ||0|000 olololololo 010-000 1 1 0 1 0 1 0 0 1 1 1 1 0 0 1 0 000000000000 000000 000001 000000000010 000000000011 000000000100 000000000101 000000000110 000000 000111 000000 001000 010000 010001 010010 010011 010100 010101 010110 010111 0 X oooooooooooooooo x X 0 0 OR AND XOR ADD NOR NAND SLT SUB JR ORI ANDI XORI ADDI NORI NANDI SLTI SUBI LW SW 0 1 0 0 0 1 O 0 1 0 0 0 0 0 0||0||0||0|00| 00|00 0 0 1 1 0 1 0 0 0 o 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 ooooooo 0 1 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 o 1 ololololo 1 0 1 0 0 0 0 0 1 1 1 1 0 1 0 0|00|0|0 | 100 | 0|0 | 0 100011 0 1 1 1 0 0 0 1 1 0 0 0 Olo 101011 0 1 1 1 0 1 0 0 110000 X X x X X 0 0 0 1 0 0 BEQ J JAL 110001 X x X X X X 0 0 1 1 110011 x X 1 0 1 0 1 0 0 1 1 Step3: Table 3 shows the Verilog program students are required to use for test. Fill-in the machine codes for this program and also load the instruction memory with this program Table 3: The content of the instruction memory Address Instruction Machine Code 00 LW LW LW LW SGT 01 02 03 04 05 06 07 08 SGTI R1, 12 (RO) R2, 4 (RO) R3, 20 (RO) R4, 28 (RO) R5, R1, R2 R8, R3, 2 R6, R3, R4 R7, R4, 9 R5, 12 (RO) R6, 4 (RO) R7, 20 (RO) R8, 28 (RO) SGT SGTI SW 09 SW 10 SW 11 SW
