In this experiment, students have to modify the design of their pipelined processor implementation in experiment $9$ to implement branch$-$if$-$greater$-$than$-$or$-$equal $($bge$)$ and load$-$upper$-$immediate $($lui$)$ instructions. Afterwards, you need to test your updated design using the program given in Table $3.$

For the implementation of the bge instruction, the instruction assembly is: bge rs$1,$ rs$2,$ immediate and the machine code is as follows:

$312524201915141211760$

imm$[12],$ imm$[10$:$5]$ rs$2$ rs$1$ Funct$3=101$ imm$[4$:$1],$ imm$[11]$ Opcode $=1100011$

The bge instruction is executed as follows:

if $(($rs$1)>=($rs$2))$

PC $=$ target address $=$ PC of bge $+$ sign$-$extend$($imm$)*2$

else

PC $=$ PC $+4$

For the implementation of the lui instruction, the instruction assembly is: lui rd$,$ immediate and the machine code is as follows:

$311211760$

imm$[31$:$12]$ rd Opcode $=0110111$

The lui instruction is executed as follows:

$($rd$)=\{$imm$[31$:$12],12$b$0\}$

Take into consideration the following hints:

$$ Similar to the beq instruction, the bge instruction should be resolved in the ID stage. Hence, if the bge instruction is taken then the instruction in the IF stage must be flushed.

$$ Similar to the R$-$type and I$-$type instructions, the result of lui instruction can be forwarded from the MEM or the WB stage. The tables below show examples of these cases:

Clock Cycle $123456$

LUI X$5,100$

F D E M

W

ADD X$7,$ X$5,$ X$6$

F D E M W

Clock Cycle $1234567$

LUI X$5,100$

F D E M W

ADD X$7,$ X$3,$ X$2$ F D E M W

ADDI X$9,$ X$5,129$

F D E M W

Unlike previous experiments, this is not a guided experiment, i$.$e$.,$ students are free to make decisions on how to modify all modules in their processor. However, you are not allowed to remove any of the old instructions or start a new implementation from scratch. Students are expected to extend their processor implementation in the lab. In addition, you are free to choose between structural or behavioral modeling for your modifications.

Step$1$: In Table $1,$ describe the changes you did for each file $($if any$).$ Note that there are some files where modifications are not needed.

Table $1$: Verilog files

File Modified $($yes$/$no$)?$ Changes Description

Library$439.$v no

Exp $2$ FA and MUX$8\_1.$v

Exp $2$ ALUs.v

Exp $3$ REG$32$ and MUX$32\_1.$v no

Exp $3$ Decoders and RegFile.v no

Instruction$\_$memory.v yes Loaded the program in Table $3$

DataMem.v no

ControlUnit.v

Exp$6$ modules.v

Exp$7$ modules.v

Exp$8$ modules.v

Exp$9$ modules.v

Piplining$\_$Procssor.v

$$

Step$2$: In Table $2,$ complete the new rows added for the bge and lui instructions. In case new control signals are needed, use the extra three columns given to show your changes to the control unit. Highlight your changes in yellow, bold color. You can also add new columns if needed.

Table$2$: Truth Table for the Control Unit

instruction opcode func$3$ func$7$ aluop$[2]$ aluop$[1]$ aluop$[0]$ alusrc pcsrc$[1]$ pcsrc$[0]$ memtoreg$[1]$ memtoreg$[0]$ regwrite memread memwrite branch

OR $01100111100000000000000001000$

AND $01100111110000000001000001000$

XOR $01100111000000000010000001000$

ADD $01100110000000000011000001000$

SLT $01100110100000000110000001000$

SUB $01100110000100000111000001000$

ORI $0010011110-000100001000$

ANDI $0010011111-001100001000$

XORI $0010011100-010100001000$

ADDI $0010011000-011100001000$

SLTI $0010011010-110100001000$

LW $0000011010-011100011100$

SW $0100011010-011100$ x x $0010$

BEQ $1100011000-$ x x x x $00$ x x $0001$

BGE $1100011101-$

JAL $1101111--$ x x x x $0110100$ x

JALR $1100111000-01111010100$ x

LUI $0110111--$

$$

Step$3$: Table $3$ shows the Verilog program students are required to use for test. Fill$-$in the machine codes for this program and also load the instruction memory with this program.

Table $3$: The content of the instruction memory

Address Instruction Machine Code

$00$ LW X$1,12($X$0)$

$01$ LW X$2,4($X$0)$

$02$ LW X$3,100($X$0)$

$03$ LUI X$5,5$

$04$ ADD X$6,$ X$3,$ X$5$

$05$ LUI X$5,-1$

$06$ ADDI X$9,$ X$0,3$

$07$ ADDI X$7,$ X$5,2048$

$08$ BEQ X$3,$ X$6,4$

$09$ BGE X$6,$ X$3,8$

$10$ ADDI X$7,$ X$0,25$

$11$ SW X$6,23($X$7)$

$12$ JALR X$1,60($X$0)$

$13$ XOR X$0,$ X$1,$ X$2$

$14$ BGE X$1,$ X$9,-8$

$15$ LW X