In this part of the procedure, you will need to use an example to understand the function of the DRAM Identify the input and output signals of the DRAMs You can use commercial data sheets as examples Walk through bit by bit (consider each bit takes one clock cycle) the function of the DRAM using the example 01111100111111100001011110101 as input sequence for writing data Draw a schematic flowchart of the DRAM, Use the example you walked through in step 2 to test your flowchart and make any necessary revision correction You should at this point notice that a sub circuit for this DRAM must be designed to inform the circuit that supplies the DRAM next input to stall and not apply a new input for one clock cycle This means that other than the output message sequence, you will need another sequence as the output to feedback to the circuit that supplies the DRAM input to know when to stall (You may assume that the circuit that supplies the DRAM input sequence is already designed and does stall correctly according to the indication provided by the DRAM to do so )

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In this part of the procedure, you will need to use an example to understand the function of the DRAM.

Identify the input and output signals of the DRAMs. You can use commercial data sheets as examples.
Walk through bit by bit (consider each bit takes one clock cycle) the function of the DRAM using the example 01111100111111100001011110101 as input sequence for writing data.
Draw a schematic flowchart of the DRAM,
Use the example you walked through in step 2 to test your flowchart and make any necessary revision/correction.
You should at this point notice that a sub-circuit for this DRAM must be designed to inform the circuit that supplies the DRAM next input to stall and not apply a new input for one clock cycle. This means that other than the output message sequence, you will need another sequence as the output to feedback to the circuit that supplies the DRAM input to know when to stall. (You may assume that the circuit that supplies the DRAM input sequence is already designed and does stall correctly according to the indication provided by the DRAM to do so.)