In this portion of the Lab, first design a half adder and named

For a half adder you need to implement on gate level by using one xor

Then write test bench that covers all inputs values and name the module as

Simulate the code and cover all cases to test all possible

combinations of and print out all test cases on consol.

Part$-$B

In this part we will use the half adder from Part$-$A to make a full

adder.$($by instantiation of half$\_$adder$)$ and name it full$\_$adder.v

To make a full adder we will use $2$ half adders and a OR primitive

Then write test bench that covers all inputs values and name the module as

full$\_$adder$\_$tb$.$v

Then use the command

combinations of and print out all test cases on consol.

$//$ Instantiate the Unit Under Test $($UUT$)$

full$\_$adder uut $($

end module;