In this problem, we are going to design a 3-bit arithmetic logic unit (ALU) adder from scratch with ONLY AND, OR, XOR, NOT gate (a) Draw the truth table for a single bit full adder and reduce its logic with k-map technique Sketch the logic network. (b) Sketch the logic network for a 3-bit full adder with single bit full adders. (c) Modify the structure to support subtraction Modify the structure to support overflow trigger