In this problem, you are required to design a finite state machine (FSM) preferably MOORE to compare two 3-bit numbers x and y (represented as x2x1x0 and y2y1y0).

The FSM takes one bit from each number (xi and yi) as input in every clock cycle.

Assume that the bits are being fed in from MSB to LSB (x2 and y2 are provided in the first cycle, x1 and y1 in the second cycle, x0 and y0 in the third cycle).

The FSM produces a 2-bit output as follows:

(i) 00, if x and y are equal,

(ii) 01, if x is greater than y,

(iii) 10 if x is less than y.

Draw the state transition diagram for this FSM.