In Verilog code:

1. Clock divider Implement a clock divider that can generate a output signal based on clk and gives you HI cycles of high and LO cycles of low. Name the simulation set to be clock_divider_test Start with the following code module clock-divider #(parameter SIZE = 4, HI = 5, LO = 5) input clk, reset, output reg out): endmodule When reset, output should start with high. Write a test module demonstrate the clock divider's behavior 1. Clock divider Implement a clock divider that can generate a output signal based on clk and gives you HI cycles of high and LO cycles of low. Name the simulation set to be clock_divider_test Start with the following code module clock-divider #(parameter SIZE = 4, HI = 5, LO = 5) input clk, reset, output reg out): endmodule When reset, output should start with high. Write a test module demonstrate the clock divider's behavior