In Verilog, Complete the controller for the Fibonacci Sequence Generator. The test bench will check for the sequence: 1, 1, 2, 3, 5, 8.

Program:

module controller( output as_ctl_t as_ctl, output shift_ctl_t shift_ctl, output logic r1_ld, r0_ld, output logic ready, input logic next, input clk, reset ); logic [2:0] step; task ctrl(logic rdy, as_ctl_t as, shift_ctl_t sh, logic r1, logic r0); begin ready <= rdy; as_ctl <= as; shift_ctl <= sh; r1_ld <= r1; r0_ld <= r0; end endtask always_ff @(posedge clk) begin if ( reset ) begin step <= 0; ctrl(0, AS_A, SH_PASS, 0, 0); end else begin case( step ) 0: begin step <= next ? 1 : 0; ctrl(0, AS_A, SH_PASS, 0, 0); end // complete the reset endcase end end endmodule

Test Bench:

`include "testbench/seq_gen.v" module main; reg16_t seq_out; logic clk, reset, ready, next; logic last_ready; as_ctl_t as_ctl; shift_ctl_t shift_ctl; logic r1_ld, r0_ld; integer expected[0:5]; integer exp, expected_count; logic pass_fail; task clock_cycle(integer n); repeat(n) begin clk = 0; #5; clk = 1; #5; end endtask task advance_state; integer cur_st; begin cur_st = CTL.step; clock_cycle(1); $display("step=%2d ready=%b R0=%4x R1=%4x as=%b sh=%b r0_ld=%b r1_ld=%b", cur_st, ready, DP.r0_v, DP.r1_v, as_ctl, as_ctl, r1_ld, r0_ld); end endtask seq_gen_dp DP( seq_out, clk, reset, as_ctl, shift_ctl, r1_ld, r0_ld); controller CTL( as_ctl, shift_ctl, r1_ld, r0_ld, ready, next, clk, reset); initial begin pass_fail = 1; expected_count = 0; expected[0] = 1; expected[1] = 1; expected[2] = 2; expected[3] = 3; expected[4] = 5; expected[5] = 8; // reset fsm clk = 0; reset = 1; advance_state; reset = 0; next = 1; while ( pass_fail && expected_count < 6 ) begin last_ready = ready; advance_state; if ( last_ready == 0 && ready == 1 ) begin exp = expected[expected_count]; if ( exp === seq_out) begin $display("found = %1d", exp); expected_count = expected_count + 1; end else begin $write("expected != seq_out: "); $display("expected=%1d seq_out=%1d", exp, seq_out); pass_fail = 0; end end end if ( pass_fail ) $display(" Test passed"); else $display(" Test failed"); $finish; end initial begin #2000 $finish; $display("Took too long."); $display(" Test failed"); end endmodule