In Verilog,build a 1s Counter circuit, ie a circuit that receives an N-bit input value, and outputs the number of 1s found in the input vector.

Complete a Verilog module to continuously receive a 255-bit input named X and Generate an 8-bit output named Num1s that reports the number of 1-bits found in X.

The transition of output Num1s must be glitch free, so when the input changes values, the output must transition directly from the old value to the new value, without first passing through a sequence of one or more incorrect values.