In VHDL, create the following 3 circuits along with a testbench for each circuit.

a) A 64 bit 4-to-1 multiplexor using the dataflow architecture

b) a 1-bit 4-to-1 multiplexor using a 1-bit 2-to-1 mutliplexers using structural architecture

c) aa 64-bit 4-to-1 multiplexer implemented using circuit b by using a generate statement