In Web2, Figure 1.a (page 13), assuming the counter has been misconfigured so that Q0 feeds into the clock input for FF1, complete the timing diagram for six clock cycles. Please draw the diagram by hand and show all steps The following is a three-bit asynchronous binary counter and its timing diagram for one cycle. It works exactly the same way as a two-bit asynchronous binary counter mentioned above, except it has eight states due to the third flip-flop. [Floyd] Figure 1.4a: Three-bit asynchronous binary counter, timing diagram, binary state sequence