initial #

Sfinish;

endmodule

Verilog module:

module test$($output $[1$:$0]Q,$ input $x,$ input clock, input reset$)$;

reg $1$:$0$ state;

parameter $SO=2^{\text{'}}b00,S1=2^{\text{'}}b01,S2=2^{\text{'}}b10,S3=2^{\text{'}}b11$;

always @ $($posedge clock, negedge reset$)$

if$($lreset$)$ state $50$;