Instruction execution design might not always result in stages that are equal in length. As an example, consider a system that can be cleanly divided into 6 stages, in the order (A, B, C, D, E, F), each with a propagation delay (in ps) of (40, 80, 100, 150, 160, 70), for a grand total of 600 ps. The register loading time is 25 ps.

(a) If you only had one extra set of registers to place between an adjacent pair of stages in order to form a 2-stage pipeline, where would you place them? Compute the minimum clock cycle time and the maximum possible CPU throughput.

(b) If you had two extra sets of registers, where would you place them to form a 3-stage pipeline? Again, compute the min clock cycle time and max throughput.

(c) If you had five extra sets of registers, and created a 6-stage pipeline, what would the min clock cycle time and max throughput be?

(d) Suppose you had two extra sets of registers, like in part (b). If you could direct your designers to divide any of A, B, C, D, E, F into two stages, where would you tell them to concentrate their efforts?