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Instruction Set Analysis and CPU Architecture We need to develop an instruction set, formats, and CPU architecture to support the following operations: MEM R1: 16

Instruction Set Analysis and CPU Architecture We need to develop an instruction set, formats, and CPU architecture to support the following operations: MEM R1: 16 instructions R3 R1 OP R2: 32 instructions R1 R1 OP R2: 32 instructions MEM R1 OP R2: 32 instructions R2 R1 OP MEM: 16 instructions The machine has 16 general purpose registers, each 16 bits in size. Memory is accessed by a base plus displacement of 12 bits. Page 3: Analysis. Page 4: Instruction Formats. Page 5 CPU internal design.

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