Answered step by step
Verified Expert Solution
Link Copied!

Question

1 Approved Answer

it is the Question and the answer please explain the answer only how we solve it Thanks Question 1: Consider an instruction set architecture with

it is the Question and the answer

please explain the answer only

how we solve it

Thanks

image text in transcribed

image text in transcribed

Question 1: Consider an instruction set architecture with the following characteristics: Memory: byte-addressable, 8-bit addresses. Numbers: unsigned or signed (two's complement). Registers (8-bit): PC, SP and two general-purpose registers (RO, and R1). Instructions (variable-length): one-operand or two-operand. o One-operand instructions (16-bit): 8-bit opcode followed by one 8-bit operand. Two-operand instructions (24-bit): 8-bit opcode followed by two 8-bit operands. o Operand (8-bit): 2-bit addressing mode (AM) followed by 6-bit value/address (VA). Addressing-mode (2-bit): 00 immediate, 01 register, 10 indexed, 11 PC- relative (where register number is encoded by the least significant bit of VA whenever is needed). Some of the supported operations: Opcode Operation Mnemonic (Decimal) Description Move MOV 8 First operand is destination. Second operand is source. Arithmetic ASR First operand specifies value to be shifted. Second operand 10 Shift Right specifies number of bit positions. Arithmetic ASL First operand specifies value to be shifted. Second operand 11 Shift Left specifies number of bit positions. First operand is the first source and the destination in the Add ADD 12 same time. Second operand is the second source. Note that the first operand cannot be a memory location. First operand is the first source and the destination in the Subtract SUB 13 same time. Second operand is the second source. Note that the first operand cannot be a memory location. Decrement DEC 14 Operand specifies value to be decremented. Increment INC 15 Operand specifies value to be incremented. Branch If First operand specifies value to be tested. Second operand Zero BRZ 48 specifies target address using PC-relative addressing mode. Branch If First operand specifies value to be tested. Second operand BRN 49 Negative specifies target address using PC-relative addressing mode. Branch BR Operand specifies target address using PC-relative 50 addressing mode. a) Translate the following C-language snippet to the assembly language of this instruction set: for(i -4; i

Step by Step Solution

There are 3 Steps involved in it

Step: 1

blur-text-image

Get Instant Access to Expert-Tailored Solutions

See step-by-step solutions with expert insights and AI powered tools for academic success

Step: 2

blur-text-image

Step: 3

blur-text-image

Ace Your Homework with AI

Get the answers you need in no time with our AI-driven, step-by-step assistance

Get Started

Recommended Textbook for

Pro PowerShell For Database Developers

Authors: Bryan P Cafferky

1st Edition

1484205413, 9781484205419

More Books

Students also viewed these Databases questions

Question

What is the Definition for Third Normal Form?

Answered: 1 week ago

Question

Provide two examples of a One-To-Many relationship.

Answered: 1 week ago