iv. Consider the 4:1 Mux shown in Figure 3.1, SV S1 SO Figure 3.1 If you are asked to design above Mux, what is the modelling approach that you would choose? Justify your selection. (04 Marks) b. Considering the synchronization with the rest of the system, now you are asked to design the above Mux using behavioural modelling. One of your colleague says you must use an always block to implement it. Why an always block is a must? (03 Marks) What are the ports that should be in the sensitivity list (Only include necessary ports)? Justify your answer. (04 Marks) d Write the Verilog code for the above Mux using behavioural modelling a pe 88F JUNI 2