Juestions 45 points Below is a list of block sequences requested by the CPU. 1.7.1.3,2 For each of these requests, given a direct mapped cache with 4 blocks, 2 way set associative cache, fully associative cache (4 way so associative cache). State whether each memory address reference is a hit or a miss, assuming the cache is initially empty Replacement Rule: LRU. Address Direct-mapped Cache: Hit/Miss 2-way associative cache Fully associative cache: Hit/Miss Hit/Miss 1 y 7 1 3 > 7 Remaining Time: 1 hour. 32 minutes, 11 seconds. Question Completion Status: 7 > Miss rate for Direct-mapped cache = %. Miss rate for 2-associative cache - %. % Miss rate for Fully associative cache = Which cache is the best in terms of hit rate? Moving to the next question prevents changes to this answer EN ve 1.10 19/-0/ TOSHIBA