juetstion 5B (20 points) pirte a description of a system that determines whether two 8-bit std_logic_vector inputs are both even or Sd parity. The entity's name is parity_comp. The input vectors are x and y. The output is the std_logic sign ane par. Signal same_par is a ' 1 ' if both input vectors are even parity or both are odd parity; otherwise, it v '. Use this function parity_even from this listing. library ieee; use ieee.std_logic_1164.all; entity parity_even_entity is port ( in_vector : in std_logic_vector(7 downto 0); even : out std_logic ): end parity_even_entity; architecture behavioral of parity_even_entity is function parity_even (s: std_logic_vector(7 downto 0)) return std_logic is variable result : std_logic := 'I'; begin for i in 7 downto 0 loop if s(i)= ' 1 ' then result := not result; end if; end loop; return result; end parity_even; begin even