June 16, 2017 1 Pipeline: A particular (fictional) CPU has the following internal units and timings 1. IFD: Instruction fetch + decode : 160 ps 2. RR: Register read : 80 ps 3. ALU : 240 ps 4. MA : memory access : 160 ps (assuming cache) 5. RW : register write : 80 ps There are 5 basic instruction types: 1. LOAD: IFD+RR+ALU+MA+RW : 720 ps 2. STORE: IFD+RR+ALU+MA : 640 ps 3. ARITHMETIC: IFD+RR+ALU+RW : 560 4. BRANCH: IFD+RR+ALU : 480 ps 5. MEMOP: IFD+RR+MA+ALU+MA: 800 ps A. What is the frequency of this machine without a pipeline? B.What is the frequency for a pipelined version of this CPU? C. What is the datapath for the pipeline - that is, what functional units in what order