Just Question 2

Q1: Consider the following MiPS assembly language code: Draw the plpeline diagram (complete the table below) showing the timing of the code instructions on the 5-stage pipeline (15, 10, EX, MEM, WB). The pipeline supports forwarding and pipeline stall, Draw an arrow showing forwarding between the stage that provides the data and the stage that recelves the data. Show all stall cycles (draw an X in the box to represent a stall cycle). Determine I):ORIS5.,5.,IT4ADOI5s),5+1+Ir:ADD$5,55,55?11:tW$5,1($51)10=ADO$5.,55+,$s.1):SW85,1(8s+) the number of clock cycles to execute this code. Q2: Draw the pipeline diagram for the code in Q1 for a 2-way multiple-issue 5-stages plpellined datapat