Lab 03- Part A: Basic Memory Components 1-Complete the following expected results table (replace? with the proper values; put an X whenever the output is invalid). Expected Table srlatch Inputs / Outputs Values 0100101 1010011 Expected Table clk-srlatch (Pay attention to the CLK pattern) Values 0100101 1010011 0101010 ?7??? Inputs/Output CLK 0 Expected Table D-latch Inputs /Outputs Values 001100110 010101010 CLK