LAB 5: To design a FIR filter with below specifications using Simulink block sets and simulate and verify the results in Hardware (FPGA) using Hardware-co-simulation. Sampling Frequency (Fs) = 1.5 MHz Fstop 1 = 270 kHz Fpass 1 = 300 kHz Fpass 2 = 450 khz Fstop 2 = 480 kHz Attenuation on both sides of the passband = 54 dB Pass band ripple = 1 LAB 5: To design a FIR filter with below specifications using Simulink block sets and simulate and verify the results in Hardware (FPGA) using Hardware-co-simulation. Sampling Frequency (Fs) = 1.5 MHz Fstop 1 = 270 kHz Fpass 1 = 300 kHz Fpass 2 = 450 khz Fstop 2 = 480 kHz Attenuation on both sides of the passband = 54 dB Pass band ripple = 1