Lab One: Logic Gates and Binary Addition The purpose of this lab is to introduce the topic of logic gates and binary addition. Both of these topics are very important to our course and digital systems. 1. Logic Gates: A Summary - All electronic gates require a DC power source (ie. battery) - For the purposes of this class all input and output bits can be represented by 0 and 5 volts. There is always only 1 logical output per a logic gate. - There is always a time delay between the input being applied and a corresponding output although for the purposes of this class we do not consider this delay - While we investigate logic gates as building blocks, which is a common approach to digital systems, in reality these are implemented as transistor logic using silicon 2. Truth Tables: A Summary - When investigating and designing digital systems there must be a way to fully understand what the system will perform in all instances. Truth tables ensure that we are able to fully understand every system in a systematic approach. - These truth tables show all combinations of logic, all possible outcomes - All inputs and outputs must be labelled and by convention inputs are always on the left and outputs on the right of the table. A bit by bit approach is taken to solve them - The number of rows is determined by the number of input bits to the power of 2 3. Logic Gates Introduced: Load the logic gate simulator software package on the school computer (or sourced from www.kolls.net/gatesim). You will notice there are logic gates, summarised as basic or compound gates, located on the left side of the screen as well as IO gates. The following activities will require you to use these gates. 3.1. One Bit Logic Gates There are 2 one bit logic gates. We can tell they are only 1 bit as there is only 1 input on the left of the gate. Build the following system in the Logic Gate Simulator using the square IO as an input switch, the circle which represents a LED, and the Inverter Gate. Assuming that OFF = 0 (white) and ON = 1 (red) we can develop a truth table that includes every possible combination of inputs and outputs for the single bit system. Fill out the table below for the inverter system that you have built. Because it is only a single bit it is either ON or OFF. Page 1 of 8 Table 1: 1 Bit Logic Gates I/P 0 1 O/P Inverter Buffer In the Logic Gate Simulator find the Buffer Gate which is the only 1 bit gate. Draw the simulated system for the buffer below and fill out the 2 missing entries in Table 1. 3.2. Two Bit Logic Gates Most logical systems will use 2 bit logic gates, or combinations of them, to perform logical functions. A. Based on the previous note that the number of rows in a truth table, which must encapsulate all possible combinations of inputs, is based on (number of bits) 2 and the fact that we are using 2 bit logic gates, how many rows should we have in a truth table for the 2 bit logic gates? _______ Build the below system which models the AND gate. Using the Logic Gate Simulator complete the AND entry in Table 2. Note the name of the input switches and their position on the table which are important for all logic systems. Build the below system which models the OR gate. Using the Logic Gate Simulator complete the OR entry in Table 2. The AND and OR gates are the two core 2 bit gates. All other logical gates can be created through a combination of AND/OR logic. Build the following system: Page 2 of 8 B. When you simulate all logical combinations for the above system did the Output at 1 change in any way from the AND logic you demonstrated in Table 2? ______________ C. The Output at 2 is the NAND logic. Complete Table 2 for the NAND entry. This is the Negated AND gate which is facilitated by the Inverter Gate. D. Using this concept build and draw the NOR logic system below using a 2 bit gate and a 1 bit gate in tandem similar to the NAND example above. Fill out Table 2 for the NOR entry. E. Using the knowledge of the expected output for NAND and NOR logic. Which symbols are available in the Logic Gate Simulator that demonstrates this logic as a single 2 bit gate? Draw and label them below. Build the following system which models both the Exclusive OR Gate (XOR) and the Exclusive NOR Gate (XNOR). Fill out the appropriate entries in Table 2 for both logical systems. Table 2: 2 Bit Logic Gates I/P B A 0 0 0 1 1 0 1 1 O/P AND OR NAND Page 3 of 8 NOR XOR XNOR 3.3. Binary Addition Theory As discussed today in class the rules and properties of addition apply regardless of what base the operation is being performed in. As a review: A. What single digit values can be used to represent decimal? ____________ B. What is the largest single digit value that can be used in decimal? ____________ C. What single digit values can be used to represent binary? ____________ D. What is the largest single digit value that can be used in binary? ____________ When we add the largest single digit in decimal (9) with any other non-zero decimal number we are unable to store the result in a single place value. At this transition point, for example 9+1, we are increasing the size of the number through a new place value and resetting the existing place value to be null as the solution is 10. Binary works the same way however due to the limited range of values in base 2 we can develop 4 rules of binary addition as seen in class. E. If you had two 1 bit numbers, which we will call A and B, how many ways can these be added together? Demonstrate all of them below. Hint: We are looking for unique combinations which are similar to the truth tables provided with the logic gates above. F. Are any of these cases similar? What property of addition can be used to describe any similarities? How many unique combinations of possibilities are there for base 2 addition? G. These permutations of 2 bit addition can be used to develop 3 rules of addition. Summarise the three unique cases from the above combinations labelling them rules 1 through 3. H. The forth rule of binary addition can be developed by adding a carry condition or a third input bit. Using a 3rd bit, called Cin, what possible new combinations exist when adding to A and B when they are both 0`s or 1`s? Page 4 of 8 3.4. Binary Addition Simulation As introduced in class we will use logic gate simulation to demonstrate the 4 rules of binary addition like the computer does internally. 3.4.1 Stand Alone Rules Using the three rules of binary addition that you developed in G above, and the concepts of logic gates above, build a circuit for each of your rules. Draw each individual circuit below. Ensure you label which rule you are modelling, input bits, and output functions. 3.4.2 Half Adder The following circuit uses a combination of AND, OR, and inverter gates to perform binary addition similar to your systems above but as a single unit. Build the following circuit in the Logic Gate Simulator. Note that there are and can only be 2 switches controlling the inputs A and B. A. Using the above circuit develop a truth table that encapsulates all possible input and output combinations. Ensure that you label the inputs and outputs on your table. B. From your 4 rules of binary addition can you successfully implement them all with the half adder? Why or why not? __________________________________________________ Page 5 of 8 The half adder circuit provided above can be simplified using the gates investigated earlier in the lab. Using the simulation software, and your logical outputs from Table 1 and 2, how can you reduce the number of gates yet still maintain all existing functionality? Provide the reduced circuit below. 3.4.3 Full Adder There are many logical combinations that can be used to perform binary addition on the computer. Above we looked at the half adder which is a simplistic design. Below is a more complex system known as the full adder. Build this system in the simulation software. A. Using the full adder and the simulation software develop the truth table for the system. Page 6 of 8 B. Considering the half adder that you have previously built, and the fact that the full adder has an extra input bit, what does this carry in bit have to be set to have the system perform the same as the half adder? C. Add 01012+11002 below by hand. What is the result? D. Did you need to add more than 2 bits together manually at any single point in time? E. For this manual operation performed in D, could you use the half adder to implement this specific step? F. For this manual operation performed in D, could you use the full adder to implement this specific step? What is the difference between the full and half adders? Page 7 of 8 G. Using the above full adder how can you expand this to perform the 4 bit addition in part C so that instead of doing it step by step you can apply it to one adder unit? Draw the high level idea below using a block diagram. Hint: How many bits are each number and think about how many switches you need per bit. H. If you are done the above system, design the same function for the full adder simplifying it using XOR and AND gates. It will be much \"cleaner\" than the full adder provided above. Page 8 of 8