"library IEEE;

use ieee.std$\_$logic$\_1164.$all;

use IEEE.numeric$\_$std$.$all;

use work.subccts.all;

entity bitbreaker is

port$($ SW : in std$\_$logic$\_$vector$(9$ downto $0)$;

KEY : in std$\_$logic$\_$vector$(0$ to $2)$;

HEX$0$ : out std$\_$logic$\_$vector$(0$ to $6)$;

HEX$1$ : out std$\_$logic$\_$vector$(0$ to $6)$;

HEX$2$ : out std$\_$logic$\_$vector$(0$ to $6)$;

HEX$3$ : out std$\_$logic$\_$vector$(0$ to $6)$;

LED : out std$\_$logic$\_$vector$(9$ downto $0))$;

end bitbreaker;

architecture mixed of bitbreaker is

$--$ signals associated with ports as illustrated in Figure $1$

signal ledCntrl, reset, start, load, clk : std$\_$logic;

signal guess, guessChk : std$\_$logic$\_$vector$(7$ downto $0)$;

signal targetLo : std$\_$logic$\_$vector$(0$ to $6)$;

signal targetHi : std$\_$logic$\_$vector$(0$ to $6)$;

signal guessLeft : std$\_$logic$\_$vector$(0$ to $6)$;

signal bitsCorrect : std$\_$logic$\_$vector$(0$ to $6)$;

$--$ ADD YOUR SIGNALS AS NEEDED BELOW THIS LINE

TYPE state$\_$t is $($init$,$ display, saved, gameEnd$)$;

signal curr$\_$s$,$ next$\_$s: state$\_$t;

begin

$--$ associate ports with player signals as illustrated in Figure $1$

start $<=$ not KEY$(0)$;

load $<=$ not KEY$(1)$;

clk $<=$ KEY$(2)$;

guess $<=$ SW$(7$ downto $0)$ ;

reset $<=$ SW$(8)$;

ledCntrl $<=$ SW$(9)$;

HEX$0<=$ targetLo;

HEX$1<=$ targetHi;

HEX$2<=$ guessLeft;

HEX$3<=$ bitsCorrect;

WITH ledCntrl SELECT

LED$(9$ DOWNTO $0)<="00"$ & guessChk WHEN $\text{'}0\text{'},$

$"000000"$ & reset & clk & load & start WHEN OTHERS;

$--$ ADD YOUR CONTROL PATH BELOW

$--$targetLo $<=$ SW$(3$ downto $0)$;

$--$targetHi $<=$ SW$(7$ downto $4)$;

$--$ Include your FSM transitions

$--$TYPE state$\_$t IS $($init$,$ display, saved, gameEnd$)$;

$--$signal next$\_$s: state$\_$t;

$--$ Include your FSM output signals

process$($curr$\_$s$,$ next$\_$s$,$ reset, start, load$)$

begin

CASE curr$\_$s IS

when init $=>$

if start $=\text{'}0\text{'}$ then

next$\_$s $<=$ init;

else

guessLeft $<="8"$;

bitsCorrect $<=($others $=>\text{'}0\text{'})$;

guessChk $<=($others $=>\text{'}0\text{'})$;

targetHi $<=$ SW$(7$ downto $4)$;

targetLo $<=$ SW$(3$ downto $0)$;

next$\_$s $<=$ display;

end if;

when display $=>$

$--$correct bits

seg$7\_$port: seg$7$ PORT MAP$($bitsCorrect$,$ HEX$3)$;

$--$guesses left

seg$7\_$port: seg$7$ port map$($guessLeft$,$ HEX$2)$;

$--$guess hi

seg$7\_$port: seg$7$ port map$($targetHi$,$ HEX$1)$;

$--$guess lo

seg$7\_$port: seg$7$ port map$($targetLo$,$ HEX$0)$;

$--$if loaded

if load $=\text{'}0\text{'}$ then

next$\_$s $<=$ display;

else

next$\_$s $<=$ saved;

end if;

$--$else stay here

when saved $=>$

$--$change guess hi and lo

targetHi $<=$ SW$(7$ downto $4)$;

targetLo $<=$ SW$(3$ downto $0)$;

$--$find correct bits

bitsCorrect $<=$ match$8$ port map$($SW$(7$ downto $0),$ guessChk, bitsCorrect$)$;

$--$guesses left $--$;

if guessLeft $>\text{'}0\text{'}$ then

guessLeft $<=$ guessLeft $-1$;

else

guessLeft :$=\text{'}0\text{'}$;

end if;

$--$game end or display

if guessLeft $=\text{'}0\text{'}$ then

next$\_$s $<=$ gameEnd;

elsif bitsCorrect $=\text{'}8\text{'}$ then

next$\_$s $<=$ gameEnd;

else

next$\_$s $<=$ display;

end if;

when gameEnd $=>$

$--$correct bits

seg$7$ port map$($bitsCorrect$,$ HEX$3)$;

$--$guesses left

seg$7$ port map$($guessLeft$,$ HEX$2)$;

$--$guess hi

seg$7$ port map$($targetHi$,$ HEX$1)$;

$--$guess lo

seg$7$ port map$($targetLo$,$ HEX$0)$;

END CASE;

end process;

process$($clk$,$ reset$)$

begin

if reset $=\text{'}0\text{'}$ then

curr$\_$s $<=$ init;

elsif$($clk$\text{'}$event and clk $=\text{'}1\text{'})$ then

curr$\_$s $<=$ next$\_$s;

end if;

end process;

end architecture;" $"--$

$--$ seg$7$: drives a $7-$segment display with a $4-$bit binary value

$--$

LIBRARY ieee ;

USE ieee.std$\_$logic$\_1164.$all ;

ENTITY seg$7$ IS

PORT $($ bin : IN STD$\_$LOGIC$\_$VECTOR$(3$ DOWNTO $0)$ ;

segments : OUT STD$\_$LOGIC$\_$VECTOR$(0$ TO $6))$ ;

END seg$7$ ;

ARCHITECTURE Behavior OF seg$7$ IS

BEGIN

PROCESS $($ bin $)$

BEGIN

CASE bin IS $--0123456$

WHEN $"0000"=>$ segments $<="0000001"$ ;

WHEN $"0001"=>$ segments $<="1001111"$ ;

WHEN $"0010"=>$ segments $<="0010010"$ ;

WHEN $"0011"=>$ segments $<="0000110"$ ;

WHEN $"0100"=>$ segments $<="1001100"$ ;

WHEN $"0101"=>$ segments $<="0100100"$ ;

WHEN $"0110"=>$ segments $<="0100000"$ ;

WHEN $"0111"=>$ segments $<="0001111"$ ;

WHEN $"1000"=>$ segments $<="0000000"$ ;

WHEN $"1001"=>$ segments $<="0000100"$ ;

WHEN $"1010"=>$ segments $<="0001000"$ ;

WHEN $"1011"=>$ segments $<="1100000"$ ;

WHEN $"1100"=>$ segments $<="0110001"$ ;

WHEN $"1101"=>$ segments $<="1000010"$ ;

WHEN $"1110"=>$ segments $<="0110000"$ ;

WHEN $"1111"=>$ segments $<="0111000"$ ;

WHEN OTHERS $=>$ segments $<="-------"$ ;

END CASE ;

END PROCESS ;

END Behavior ;$"$ "Error $(10500)$: VHDL syntax error at bitbreaker.vhd$(102)$ near text "entity"; expecting $"(",$ or an identifier $("$entity$"$ is a reserved keyword$),$ or a sequential statement

Error $(10500)$: VHDL syntax error at bitbreaker.vhd$(102)$ near text "PORT"; expecting $"(",$ or $"\text{'}",$ or $"."$

Error $(10500)$: VHDL syntax error at bitbreaker.vhd$(102)$ near text $"$;$"$; expecting $"$:$=",$ or $"<="$

Error $(10500)$: VHDL syntax error at bitbreaker.vhd$(104)$ near text "port"; expecting $"(",$ or $"\text{'}",$ or $"."$

Error $(10500)$:$"$