library IEEE;

use ieee.std$\_$logic$\_1164.$ALL;

use IEEE.numeric$\_$std$.$all; $--$ any package with overloaded add and subtract

entity Scoreboard is

port $($

clk$,$ rst$,$ inc, dec: in std$\_$logic;

$--$ bcd$1\_$out, bcd$0\_$out : out unsigned$(3$ downto $0)$;

seg$7$disp$1,$ seg$7$disp$0$: out unsigned$(6$ downto $0)$

$)$;

end Scoreboard;

architecture Behavioral of Scoreboard is

signal State: integer range $0$ to $1$;

signal BCD$1,$ BCD$0$: unsigned$(3$ downto $0)$ :$="0000"$; $--$ unsigned std$\_$logic vector

signal rstcnt: integer range $0$ to $4$ :$=0$;

type sevsegarray is array $(0$ to $9)$ of unsigned$(6$ downto $0)$;

constant seg$7$Rom: sevsegarray :$=$

$("0111111","0000110","1011011","1001111","1100110",$

$"1101101","1111100",$

$"0000111","1111111","1100111")$; $--$ active high with "gfedcba" order

signal count: integer :$=1$;

signal tmp: std$\_$logic :$=\text{'}0\text{'}$;

signal clock$\_$out: std$\_$logic :$=\text{'}0\text{'}$;

begin

$--$ bcd$1\_$out $<=$ bcd$1$;

$--$ bcd$0\_$out $<=$ bcd$0$;

process $($clk$,$ tmp$)$

begin

if $($clk$\text{'}$event and clk $=\text{'}1\text{'})$ then

count $<=$ count $+1$;

if $($count $=10000000)$ then

tmp $<=$ NOT tmp;

count $<=1$;

end if;

end if;

clock$\_$out $<=$ tmp;

end process;

process $($clock$\_$out$)$

begin

if clock$\_$out'event and clock$\_$out $=\text{'}1\text{'}$ then

case State is

when $0=>--$ initial state

BCD$1<="0000"$; BCD$0<="0000"$; $--$ clear counter

rstcnt $<=0$; $--$ reset RESETCOUNT

State $<=1$;

when $1=>--$ state in which the scoreboard waits for inc and dec

if rst $=\text{'}1\text{'}$ then

if rstcnt $=4$ then $--$ checking whether $5$th reset cycle

State $<=0$;

else rstcnt $<=$ rstcnt $+1$;

end if;

elsif inc $=\text{'}1\text{'}$ and dec $=\text{'}0\text{'}$ then

rstcnt $<=0$;

if BCD$0<"1001"$ then

BCD$0<=$ BCD$0+1$; $--$ library with overloaded $"+"$ required

elsif BCD$1<"1001"$ then

BCD$1<=$ BCD$1+1$;

BCD$0<="0000"$;

end if;

elsif dec $=\text{'}1\text{'}$ and inc $=\text{'}0\text{'}$ then

rstcnt $<=0$;

if BCD$0>"0000"$ then

BCD$0<=$ BCD$0-1$; $--$ library with overloaded $"-"$ required

elsif BCD$1>"0000"$ then

BCD$1<=$ BCD$1-1$;

BCD$0<="1001"$;

end if;

elsif $($inc $=\text{'}1\text{'}$ and dec $=\text{'}1\text{'})$ or $($inc $=\text{'}0\text{'}$ and dec $=\text{'}0\text{'})$ then

rstcnt $<=0$;

end if;

end case;

end if;

end process;

$--$ seg$7$disp$0<=$ seg$7$rom$($to$\_$integer$($BCD$0))$; $--$ type conversion function from

seg$7$disp$1<=$ seg$7$rom$($to$\_$integer$($BCD$1))$; $--$ IEEE numeric$\_$std$\_$logic package used

end Behavioral;