library IEEE;

use IEEE.STD$\_$LOGIC$\_1164.$ALL;

use IEEE.STD$\_$LOGIC$\_$ARITH.ALL;

use IEEE.STD$\_$LOGIC$\_$UNSIGNED.ALL;

entity ALU is

port $($

A$,$ B : in std$\_$logic$\_$vector$(7$ downto $0)$;

Opcode : in std$\_$logic$\_$vector$(3$ downto $0)$;

cin : in std$\_$logic;

Y : out std$\_$logic$\_$vector$(7$ downto $0)$

$)$;

end ALU;

architecture Behavioral of ALU is

begin

process$($A$,$ B$,$ Opcode, cin$)$

begin

case Opcode is

when $"0000"=>$ Y $<=$ A;

when $"0001"=>$ Y $<=$ A $+1$;

when $"0010"=>$ Y $<=$ A $-1$;

when $"0011"=>$ Y $<=$ B;

when $"0100"=>$ Y $<=$ B $+1$;

when $"0101"=>$ Y $<=$ B $-1$;

when $"0110"=>$ Y $<=$ A $+$ B;

when $"0111"=>$ Y $<=$ A $+$ B $+$ cin;

when $"1000"=>$ Y $<=$ not A;

when $"1001"=>$ Y $<=$ not B;

when $"1010"=>$ Y $<=$ A and B;

when $"1011"=>$ Y $<=$ A or B;

when $"1100"=>$ Y $<=$ A nand B;

when $"1101"=>$ Y $<=$ A nor B;

when $"1110"=>$ Y $<=$ A xor B;

when $"1111"=>$ Y $<=$ A xnor B;

when others $=>$ Y $<=($others $=>\text{'}0\text{'})$;

end case;

end process;

end Behavioral;

structural vhdl description