library ieee; use ieee.std_logic_1164.all;

use ieee.numeric_std.all

; entity shiftReg8 is

port ( clk : in std_logic;

rstb : in std_logic;

Din : in std_logic;

shift: in std_logic;

dir: in std_logic;

-- 0 for left, 1 for right bout : out std_logic_vector(7 downto 0) );

end entity;

architecture behavioral of shiftReg8 is

-- -- internal signals

signal bout_sig: std_logic_vector(7 downto 0);

begin

process(clk, rstb)

begin

if (rstb = '0') then bout_sig '0');

elsif (rising_edge (clk)) then

if (shift = '0') then bout_sig

elsif(dir = '0') then bout_sig

else bout_sig

end if;

end if;

end process;

bout

end behavioral;

Modify the behavioral VHDL code for the L/R shift register to add an additional input amt(A). When A is low, the shift register shifts by 1 spot, when A is high the shift register shifts by 2 spots. Instead of shifting in Din, rotate the contents of the register. Reset should put the register in the 1001 0110 state. Provide code and a simulation