library ieee ;

use ieee.std_logic_1164.all ;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

entity timer is

port (

run_stop_in, reset_n : in std_logic;

clk : in std_logic;

led : out unsigned (3 downto 0);

alarm : out std_logic );

end timer;

architecture rtl of timer is

signal count_next : unsigned (31 downto 0) ;

signal timeleft_next : unsigned (3 downto 0) ;

signal timeleft : unsigned(3 downto 0) ;

signal count : unsigned (31 downto 0) ;

signal run_stop_rising, run, run_next : std_logic;

signal run_stop, run_stop0 : std_logic ;

begin

debounce1: entity work.sync_debounce

port map ( run_stop_in, clk, run_stop ) ;

run_stop0 <= run_stop when rising_edge(clk) ;

run_stop_rising <=

'1' when run_stop0 = '0' and run_stop = '1' else

'0' ;

run_next <=

'0' when reset_n = '0' else

not run when run_stop_rising = '1' else

run ;

run <= run_next when rising_edge(clk) ;

count_next <=

to_unsigned(49999999, 32) when count = to_unsigned(00000000, 32) or reset_n = '0' else

count - 1;

count <= count_next when rising_edge(clk);

timeleft_next <=

to_unsigned(5,4) when reset_n = '0' else

timeleft - 1 when count = to_unsigned(00000000, 32) and timeleft /= to_unsigned(0000, 4) and run = '1' else

timeleft;

timeleft <= timeleft_next when rising_edge(clk) ;

led <= timeleft;

alarm <= '1' when timeleft = to_unsigned(0000, 4) else

'0';

end rtl;

Ceate A block diagram from this code.