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List and describe 3 traditional types of computers. Describe the steps it takes to translate a program in higher - level language to form suitable

List and describe 3 traditional types of computers.
Describe the steps it takes to translate a program in higher-level language to form suitable for direct execution on a computer.
Explain the correlation between clock rate and power in microprocessors, as mentioned in the chapter.
Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their CPI (classes A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 1,2,3, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2,2,2, and 2. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 10% class A,20% class B,50% class C, and 20% class D, which is faster: P1 or P2?
a. What is the global CPI for each implementation? b. Find the clock cycles required in both cases.
Explain the difference between response time and throughput in the context of computer performance metrics. Describe the relationship between response time and throughput when making changes to a computer system, such as replacing the processor with a faster version or adding additional processors.
Assume for arithmetic, load/store, and branch instructions, a processor has CPIs of 1,12, and 5, respectively. Also assume that on a single processor a program requires the execution of 2.56E9 arithmetic instructions, 1.28E9 load/store instructions, and 256 million branch instructions. Assume that each processor has a 2 GHz clock frequency. Assume that, as the program is parallelized to run over multiple cores, the number of arithmetic and load/store instructions per processor is divided by 0.7 x (where is the number of processors) but the number of branch instructions per processor remains the same. Find the total execution time for this program on 1,2,4, and 8 processors, and show the relative speedup of the 2,4, and 8 processors result relative to the single processor result.
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