ll the following statements (Total 10 marks): (1) This is about the Entity section in VHDL program. The Entity section specifies the name of entity as well as the names and types of its and ports. (3) This is about the Architecture section in VHDL program. The Architecture section specifies the name of this architecture for a specific entity and then contains either a structural or description of the entity. (3) VHDL statements are generally concurrent, which are exception of statements inside a process, which are sequentially statements, with the statements executed (4) VHDL uses the STD_LOGIC type to represent logic values. It includes not only same as BIT but also which are needed for some specific designs. (5) In a Mealy type FSM (finite state machine), output depends on and (6). Consider the following two VHDL code fragments: PROCESS BEGIN PROCESS (Reset, Clock) BEGIN WAIT UNTIL (Clock EVENT AND Clock '1); IF reset-1' THEN IF reset-'1' THEN Q2