Logic gates and timing

For the circuit below, assume the propagation delay of all gates and DFFs = 2 ns, setup time for the DFF = 3 ns, and hold time = 1 ns. What is the smallest clock period for which the circuit will operate properly? Assume RESET = 1 for 5 clock cycles. What values do S0 and S1 take? Assume RESET = 0 and you initialize S0 to 1 and S1 to 1. What new values do S0 and S1 take in the next clock cycle