Looking at the diagram below, why is it important to add the latch to IO/M, RD, and WR when it doesnt do any demultiplexing?

OE IO/M RD WR 244 IOM RD WR Buffered control hus OE AUS As AIS As 373 A, Ais A, ALE G 8088 A19 A4 As A A. A. A, 244 As Aja As A A. A, A. A, Buffered address bus OF A A A, A Az A ALE G 373 OE AD, AD AD AD AD AD AD AD DT/R DEN A B B A, B, A, B. 245 A, B A, B A B A B G DIR D D. D D D D D D Buffered data bus