May I have the solutions and answer for these questions? Thank you.

4. The following numbers represent the sequence of word memory address accessed by the CPU in a 32-word main memory 1, 23,5,18,9,4,10,20,0,3,9,13,6,12, 16,7 i Assume that a direct mapped cache with a 4-line capacity with 2-word block has some initial data. Label each reference in the list as a hit or a miss (compulsorylcapacity/conflict) and show the contents of the cache in the table in APPENDIX III 7 marks] i. What type of locality is a direct mapped cache is exploiting to improve memory access speed? Explain your answer 12 marks] ii Assume a 4-way set associative mapped cache with a 2- line capacity, 2-word block and LRU cache replacement method has some initial data. Assess each memory access reference in the list either as a hit or a miss and construct the final contents of the cache in the table in APPENDIX IV 8 marks iv. State the what type of locality a 4-way set associative mapped cache is exploiting to improve memory access speed. Explain your answer. 3 marks]